Zein

# Pseudo-target
PHONY := __build
__build:             # No operation
 
# Clear required variables
obj-y :=            # List of target files to compile
subdir-y :=          # List of subdirectories
EXTRA_CFLAGS :=      # Extra compilation options
 
# Include sibling directory Makefile
include Makefile
 
# Get the directory names of the subdirectories that need to be compiled in the current Makefile
# obj-y := a.o b.o c/ d/
# $(filter %/, $(obj-y))   : c/ d/
# __subdir-y  : c d
# subdir-y    : c d
__subdir-y  := $(patsubst %/,%,$(filter %/, $(obj-y)))
subdir-y  += $(__subdir-y)
 
# Generate the target file list for each subdirectory: target files in the subdirectory are packed into dir/built-in.o
subdir_objs := $(foreach f,$(subdir-y),$(f)/built-in.o)
 
# Filter obj-y to get the filenames in the current directory that need to be included in the program as targets
# a.o b.o
cur_objs := $(filter-out %/, $(obj-y))
# Ensure that modifying header files .h allows recompilation after re-running make (important)
dep_files := $(foreach f,$(cur_objs),.$(f).d)
# Include all dependency files
dep_files := $(wildcard $(dep_files))
ifneq ($(dep_files),)        # Not empty (i.e., there are dependency files), then execute the next operation
  include $(dep_files)  # The Make tool will read these dependency files to ensure that the Makefile knows the correct dependency relationship between source files and header files, allowing recompilation of affected source files when header files are modified
endif


PHONY += $(subdir-y)
# First target
__build : $(subdir-y) built-in.o
# Prioritize compiling content from subdirectories; -C switches to the subdirectory to execute $(TOPDIR)/Makefile.build
$(subdir-y):
  make -C $@ -f $(TOPDIR)/Makefile.build 
 
# Link subdir's built-in.o and cur_objs into the overall built-in.o target
built-in.o : $(cur_objs) $(subdir_objs)
  $(LD) -r -o $@ $^

dep_file = [email protected]
 
# Generate cur_objs target
%.o : %.c
  $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $(CFLAGS_$@) -Wp,-MD,$(dep_file) -c -o $@ $<
  
.PHONY : $(PHONY)

# The following two variables can be omitted
EXTRA_CFLAGS  := 
CFLAGS_view.o := 

obj-y += $(patsubst %.c,%.o,$(shell ls *.c))
# obj-y += subdir/

make -f custom.mk       # Specify the entry makefile

make -s           # Silent execution of command

-------------------To apply the result of the previous command to the next command, separate the two commands with a semicolon. If written on separate lines, the effect of the previous command will not be retained.
.RECIPEPREFIX = >
exec:
>  cd /home/hchen; pwd
# Prints /home/hchen

.RECIPEPREFIX = >
exec:
>  cd /home/hchen
>  pwd
# Prints /home

————————Ignore errors and do not terminate make execution
clean:
    -rm -f *.o           # Add a minus sign before the command

.IGNORE: clean           # Special target .IGNORE specifies that the clean rule ignores errors and does not terminate make execution
clean:
    rm -f *.o

make -i                  # Use -i or --ignore-errors option
make --ignore-errors

————————Only skip the current failing rule, continue executing other rules, will not terminate make execution
make -k
make --keep-going

make -p                # Output all rules and variables.
make -n                # Print the rules and commands that will be executed, but do not execute
make --debug=verbose   #
make -t                # Equivalent to UNIX touch, updates the modification date of the target to the latest, equivalent to a fake compile, just marks the target as compiled
make -q                # Check if the target exists, the return code indicates the result (0=needs updating, 2=error).
make -W <file>         # Generally specify the source file (or dependency file), Make deduces the commands to run that depend on this file based on the rules, usually used with -n to view the rule commands that occur for this file.

# Rules

A build rule consists of dependencies and commands:
target: The target file, executable file, or label to be generated
prerequisites: The source files or intermediate files that the target file depends on
command: The shell command called; usually the build tool command; must start with a tab character `Tab`; or the command can be on the same line as the dependencies, separated by `;`

When executing the `make` command, Make will:
1) Look for the Makefile or makefile file in the current directory. You can also specify a path `make -f ~/makefile`.
2) Look for the first target in the Makefile; you can also specify the target `make target`.
3) Check if the target's prerequisites (`.c/.o`) need to be updated. If the prerequisites are newer than the target or the target does not exist, execute the command.
4) Prerequisites (`.o`) may themselves also depend on other files (`.c`); Make will recursively track the dependencies of `.o` files until the final source file `.c` is compiled.
5) If there are compilation errors or missing files, Make will report an error and terminate execution; adding a `-` before the command ignores warnings about missing files and continues execution.

For example: If the `file.c` file is modified, `file.o` will be recompiled, and `edit` will be re-linked.

```Makefile
target: prerequisites; command; command
    command
    command

.RECIPEPREFIX = >
# If the current make is executed at the outermost level (MAKELEVEL= 0); define some system-related variables,
ifeq (0,${MAKELEVEL})
    cur-dir   := $(shell pwd)
    whoami    := $(shell whoami)  # Current user
    host-type := $(shell arch)    # Architecture
    MAKE := ${MAKE} host-type=${host-type} whoami=${whoami}
endif

.PHONY: all subsystem

all: subsystem   # all depends on subsystem 

subsystem:
>  $(MAKE) -C subdir MAKEFLAGS= VAR=value     # -C subdir indicates executing make in the specified directory
# or>  cd subdir && $(MAKE)

.PHONY: all

all:
    echo "Received VAR = $(VAR)"

make: Entering directory `subdir'
Received VAR = value
make: Leaving directory `subdir'

define <command package name>
<command1>
<command2>
...
endef

-------eg
.RECIPEPREFIX = >

define run-yacc
yacc $(firstword $^)    # $(firstword $^) will get the first dependency file from $^.
mv y.tab.c $@           # Rename the generated y.tab.c file to foo.c
endef

foo.c : foo.y
>  $(run-yacc)

# Change the command prefix to > instead of the default tab (tab)
.RECIPEPREFIX = >
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

# First target
edit: $(objects)
    cc -o edit $(objects)

# Rules for each target file
main.o: main.c defs.h
    cc -c main.c
kbd.o: kbd.c defs.h command.h
    cc -c kbd.c
# Other .o file rules...

.RECIPEPREFIX = >
bigoutput littleoutput: text.g
>  generate text.g -$(subst output,,$@) > $@              # Parameter replacement: $(subst output,,$@) indicates replacing output in $@ with an empty string.

# Equivalent to above
.RECIPEPREFIX = >
bigoutput: text.g
>  generate text.g -big > bigoutput

littleoutput: text.g
>  generate text.g -little > littleoutput

-------------------------------------Static pattern rules
.RECIPEPREFIX = >
<targets ...> : <target-pattern> : <prereq-patterns ...>
>  <commands>

#eg
.RECIPEPREFIX = >
objects = foo.o bar.o

all: $(objects)

$(objects): %.o: %.c                    # Matches the target file format of %.o, takes from $@ one by one; matches the dependency file format of the target set as %.c, takes from $< one by one.
>  $(CC) -c $(CFLAGS) $< -o $@

# Equivalent to above
foo.o: foo.c
>  $(CC) -c $(CFLAGS) foo.c -o foo.o

bar.o: bar.c
>  $(CC) -c $(CFLAGS) bar.c -o bar.o

# Makefile
all:
    echo $(CFLAGS)      # Passed in -O2 -Wall
    echo $(CC)

export                       # Pass all variables
export variable += value;    # Pass variable variable to the lower-level Makefile
unexport variable := value;  # Do not want variable variable to be passed to the lower-level Makefile

-----------------=  Recursive assignment: Expands the dependent variable values recursively; this assignment method is flexible, allowing for delayed variable definition, but it can lead to infinite recursive assignments, and each time the dependent variable is re-assigned, it must be recalculated.
all:
    echo $(foo)
    
foo = $(bar)
bar = $(ugh)
ugh = Huh?

-----------------:=  Immediate assignment: Expands the right-side expression at the time of assignment and stores the result in the variable, which is more efficient than recursive assignment and safer.
x := foo
y := $(x) bar    # foo bar; since it was immediately expanded, the next line does not affect the value of y.
x := later

-----------------?=  Conditional assignment: Only takes effect if the variable is undefined; does nothing if the variable is already defined, rather than overwriting the original definition.
FOO ?= bar

-----------------# Can be used not only for comments but also to mark the end of variable definitions.
dir := /foo/bar    # directory to put the frobs in

-----------------+=  Append variable value; if the original variable is defined with :=, then += is immediate assignment; if the variable is defined with =, then += is recursive assignment.
objects = main.o foo.o bar.o utils.o
objects += another.o             # Equivalent to objects = $(objects) another.o

-----------------Specify that certain variables defined in the makefile have the highest priority and will not be overwritten by command line variables passed to make.
override <variable> := <value>
override <variable> += <more text>
override <variable> = <value>

-----------------Multi-line variable definition: Similar to command packages.
define <variable>
<value>
endef

-----------------Simple replacement
${var:a=b}   # Replace the part ending with a in variable var with b.

foo := a.o b.o c.o
bar := $(foo:.o=.c) 

-----------------Pattern replacement
$(var:%.suffix1=%.suffix2)   # Replace %.suffix1 in variable var with %.suffix2.

foo := a.o b.o c.o
bar := $(foo:%.o=%.c)

-----------------------------------------Variable expressions are only effective for specific target <target> and its dependencies.
<target> : <variable-assignment>              # Variable expressions are only effective for specific target <target> and its dependencies.
<target> : override <variable-assignment>
#eg: Regardless of what the global value of CFLAGS is, the target prog and its related targets (prog.o, foo.o, bar.o) will use CFLAGS = -g.
prog : CFLAGS = -g
prog : prog.o foo.o bar.o
    $(CC) $(CFLAGS) prog.o foo.o bar.o

prog.o : prog.c
    $(CC) $(CFLAGS) prog.c

foo.o : foo.c
    $(CC) $(CFLAGS) foo.c

bar.o : bar.c
    $(CC) $(CFLAGS) bar.o

---------------------------Variable expressions are only effective for specific pattern targets.
<pattern ...>; : <variable-assignment>;
<pattern ...>; : override <variable-assignment>;
%.o : CFLAGS = -O2           # Variable expressions are only effective for targets ending with .o.

dir = foo
$(dir)_sources := $(wildcard $(dir)/*.c)        # $(dir)_sources is defined as all c files in the $(dir) directory.
define $(dir)_print                             # Even dynamically define command packages.
lpr $($(dir)_sources)                           # Print the value of $(dir)_sources.
endef

-----------------Define a variable that contains spaces
nullstring :=
space := $(nullstring)

VPATH = src:../headers       # Now look in the current directory first, then in src, and finally in ../headers.

vpath <pattern> <directories>
vpath %.h ../headers     # When not found in the current directory; search for all files ending with .h in the ../headers directory; .. is the parent directory.
vpath %.c foo            # For .c files, search in the order of "foo", "blish", "bar" directories.
vpath %   blish
vpath %.c bar

objects := $(wildcard *.o)                        # Expand the wildcard *.o, listing all .o files.

$(patsubst %.c,%.o,$(wildcard *.c))               # Replace the %.c string with %.o string, listing all .o files corresponding to .c files.

objects := $(patsubst %.c,%.o,$(wildcard *.c))    # Compile and link all .c and .o files.
foo : $(objects)
>  cc -o foo $(objects)

.RECIPEPREFIX = >
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit: $(objects)
    cc -o edit $(objects)

# Automatic deduction rules, make will deduce these rules.
main.o: defs.h
kbd.o: defs.h command.h
command.o: defs.h command.h
# Other rules...

.RECIPEPREFIX = >
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit: $(objects)
    cc -o edit $(objects)

# Merge dependencies for multiple files
$(objects): defs.h
kbd.o command.o files.o: command.h
display.o insert.o search.o files.o: buffer.h

.PHONY: clean
clean:
    rm edit $(objects)

#eg: Overloading the built-in .c to .o rule using Pattern Rules
%.o : %.c
    $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

%.o : %.s    # Cancel the built-in implicit rule, just don't write a command after it.

-include other.make *.mk $(othermake)         # Can be file names or use wildcards.

sinclude other.make *.mk $(othermake)         # Same as above.

.RECIPEPREFIX = >
.PHONY: cleanall cleanobj cleandiff

cleanall: cleanobj cleandiff
>  rm -f program

cleanobj:
>  rm -f *.o

cleandiff:
>  rm -f *.diff

.RECIPEPREFIX = >

sources = foo.c bar.c

%.d: %.c
>  @set -e; rm -f $@; \                                     # @set -e sets the script to exit immediately if an error occurs (command return value is non-zero); rm -f $@ deletes the existing intermediate file.
    $(CC) -M $(CPPFLAGS) $< > $@.$$$$; \                    # Build dependencies one by one from %.c, redirecting to a temporary file $@.$$$$, equivalent to %.d.$$$$.
    sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \   # < $@.$$$$ indicates reading input from the file %.d.$$$$; the replaced content is output to %.d; this step is for automatically updating sub.d.
    rm -f $@.$$$$
    
include $(sources:.c=.d)            # Replace all .c strings in the variable $(sources) with .d; then include the dependency relationships.

.INTERMEDIATE: mid         # Explicitly declare that the mid file is an intermediate target. Make will not treat it as a final target; after generating the mid file, it will not be automatically deleted.
.SECONDARY: sec            # sec file is an intermediate target, but make will not delete it after generating the final target.
.PRECIOUS: %.o             # Instruct make to preserve all .o files, even if they are intermediate targets.

<conditional-directive>
<text-if-true>             #
else
<text-if-false>
endif

-----------------ifeq and ifneq
.RECIPEPREFIX = >
foo = bar

ifeq ($(foo),bar)
>  echo "foo is bar"
endif

ifneq ($(foo),baz)
>  echo "foo is not baz"
endif

-----------------ifdef and ifndef
.RECIPEPREFIX = >
foo = bar

ifdef foo
>  echo "foo is defined"
else
>  echo "foo is not defined"
endif

$(<function> <arguments>)
${<function> <arguments>}

# <function> is the function name; <arguments> are parameters, separated by commas; the function name and parameters are separated by spaces.

$(subst <from>,<to>,<text>)   # String replacement: Replace <from> in the string <text> with <to>; and return.
#eg: $(subst ee,EE,feet on the street) 

$(patsubst <pattern>,<replacement>,<text>)   # String replacement: Replace <pattern> in the string <text> with <replacement>; and return.
#eg: $(patsubst %.c,%.o,x.c.c bar.c) 

$(strip <string>)   # Remove leading and trailing spaces from the string.
#eg: $(strip  a b c  ) 

$(findstring <sub_text>,<text>)   # Find the substring <sub_text> in the string <text>.
#eg: $(findstring a,a b c) # Return value: a

$(filter <pattern...>,<text>)   # Filter out parts of <text> that match the format <pattern...>.
#eg: $(filter %.c %.s,bar.c baz.s ugh.h) 

$(filter-out <pattern...>,<text>)   # Filter out parts of <text> that do not match the format <pattern...>.
#eg: $(filter-out main1.o main2.o,main1.o foo.o main2.o) 

$(sort <list>)   # Sort and deduplicate.
#eg: $(sort foo bar lose foo) 

$(word <n>,<text>)   # Extract the nth word from <text>.
#eg: $(word 2,foo bar baz)  # Extracted bar.

$(wordlist <start>,<end>,<text>)   # Extract a range of words.
#eg: $(wordlist 2,3,foo bar baz)  # Return value: bar baz.

$(words <text>)   # Count the number of words.
#eg: $(words foo bar baz)    # Return value: 3.

$(firstword <text>)   # Get the first word.
#eg: $(firstword foo bar) 

$(dir <path...>)            # Extract the directory part.
#eg: $(dir src/foo.c hacks) # Return value: src/ ./ 

$(notdir <path...>)      # Extract the non-directory part.
#eg: $(notdir src/foo.c hacks)      # Return value: foo.c hacks.

$(suffix <names...>)      # Extract the file suffix.
#eg: $(suffix src/foo.c src-1.0/bar.c hacks) # Return value: .c .c.

$(basename <names...>)      # Extract the file prefix.
#eg: $(basename src/foo.c src-1.0/bar.c hacks)    # Return value: src/foo src-1.0/bar hacks.

$(addsuffix <suffix>,<names...>)      # Add suffix <suffix> to the files in <names...>.
#eg: $(addsuffix .c,foo bar)          # Return value: foo.c bar.c.

$(addprefix <prefix>,<names...>)      # Add prefix <prefix>.
#eg: $(addprefix src/,foo bar)        # Return value: src/foo src/bar.

$(join <list1>,<list2>)      # Join two lists.
#eg: $(join aaa bbb,111 222 333)     # Return value: aaa111 bbb222 333.

$(foreach <var>,<list>,<text>)            # Loop processing of the list: Take words from <list> one by one, assign them to <var>, and then calculate using the expression <text>, ultimately returning a string with each calculation result joined by spaces.
#eg: files := $(foreach n,a b c d,$(n).o)     # Return value: a.o b.o c.o d.o.

$(if <condition>,<then-part>,<else-part>)      # Conditional judgment  
#eg: $(if 1,yes,no)     #yes.

$(call <expression>,<parm1>,<parm2>,...)      # Custom function call: Use placeholders $(1), $(2), etc. to represent parameters, pass them to <expression> for calculation and return.
#eg: 
reverse = $(2) $(1)
foo = $(call reverse,a,b) 
# Return value: b a.

$(origin <variable>)      # Check the source of the variable.
#Return value:
undefined:    Undefined.
default:      Default definition.
environment:  Environment variable.
file:         Defined in Makefile.
command line: Command line definition.
override:     Override definition.
automatic:    Automatic variable.

$(shell <command>)      # Execute Shell command.
#eg: files := $(shell echo *.c) 

$(error <text...>)      # Terminate make execution and display the specified error message.
#eg: Check if the variable is empty.
MY_VAR :=

ifeq ($(MY_VAR),)
$(error MY_VAR is not defined or is empty)
endif

$(warning <text...>)      # Output a warning, but does not interrupt the build process.
#eg: Output debugging information.
MY_VAR :=

ifeq ($(MY_VAR),)
$(warning MY_VAR is not defined or is empty)
endif

#eg: Package all .o files into the foolib function library.
foolib(*.o) : *.o
    ar cr foolib *.o

<PROJECT_NAME >/
├── build/          # Stores compiled target files, dependency files, etc.
├── bin/            # Stores the final generated executable files.
├── inc/            # Stores header files.
├── lib/            # Stores library files.
├── src/            # Stores source code files (.c).
├── tests/          # Stores test code.
├── submodule1/     # First submodule.
│   └── Makefile    # Makefile for the submodule.
├── submodule2/     # Second submodule.
│   └── Makefile    # Makefile for the submodule.
├── Makefile        # Top-level Makefile.
└── <Other files>   # May include other documents, configuration files, etc.

.RECIPEPREFIX = >
# -------------------------------
# General settings
# -------------------------------
PROJECT_NAME := 
VERSION := 1.0.0

INC_DIR := inc
SRC_DIR := src
LIB_DIR := lib
BIN_DIR := bin
TEST_DIR := tests
BUILD_DIR := build
SUBMODULES := submodule1 submodule2
INSTALL_DIR := /usr/local/bin
TAR_FILE := $(PROJECT_NAME)-$(VERSION).tar.gz

# -------------------------------
# Compiler and flags
# -------------------------------
CC := cc
CXX := g++
AR := ar
AS := as
CO := co
CPP := $(CC) -E
LEX := lex
YACC := yacc
MAKEINFO := makeinfo
      
CFLAGS := -Wall -Wextra -Og
LIBS := 
ARFLAGS := rv
ASFLAGS := 
CXXFLAGS := 
COFLAGS := 
CPPFLAGS := 
LDFLAGS := 
LFLAGS := 
YFLAGS :=

# -------------------------------
# Non-independent build loading submodule Makefile (i.e., treat submodules as static libraries and source code); independent builds for each module do not require this.
# -------------------------------
#-include $(foreach submodule, $(SUBMODULES), $(submodule)/Makefile)

# -------------------------------
# Top level Files
# -------------------------------
SRCS := $(shell find $(SRC_DIR) -name '*.c')
OBJS := $(patsubst $(SRC_DIR)/%.c, $(BUILD_DIR)/%.o, $(SRCS))
DEPS := $(OBJS:.o=.d)

# -------------------------------
# Targets
# -------------------------------
.PHONY: all clean install print tar dist TAGS test $(SUBMODULES) # Should also add a target to check if related tools are installed.

all: $(PROJECT_NAME)

# Build the main target executable
$(PROJECT_NAME): $(OBJS) $(SUBMODULES)
> $(CC) $(OBJS) -o $(BIN_DIR)/$@ $(LDFLAGS) $(LIBS)

# Build submodules: Iterate through submodules, enter them and execute make; if no makefile is found, print skip.
$(SUBMODULES):
> @$(foreach submodule, $(SUBMODULES), \
    $(MAKE) -C $(submodule) || echo "Skipping $(submodule)";)

# Automatically generate dependency files
-include $(DEPS)

# Clean target: remove build artifacts
clean:
> rm -rf $(BUILD_DIR) $(BIN_DIR) $(LIB_DIR) $(TAR_FILE)
> $(foreach submodule, $(SUBMODULES), $(MAKE) -C $(submodule) clean || echo "Skipping $(submodule)";)

# Install target: install the program
install: all
> install -m 755 $(BIN_DIR)/$(PROJECT_NAME) $(INSTALL_DIR)

# Print target: list modified source files
print:
> @echo "Modified source files since last build:"
> @find $(SRC_DIR) -type f -newer $(BIN_DIR)/$(PROJECT_NAME) -print || echo "No modified source files."

# Tarball target: create a source tarball
tar:
> tar -cvzf $(TAR_FILE) $(SRC_DIR) $(INC_DIR) $(LIB_DIR) Makefile $(SUBMODULES)

# Dist target: compress the tarball
dist: tar
> gzip $(TAR_FILE)

# TAGS target: generate ctags or etags
TAGS:
> ctags -R $(SRC_DIR) $(INC_DIR) $(SUBMODULES)

# Test target: run unit tests (assuming a separate test suite)
test:
> @echo "Running tests..."
> $(MAKE) -C $(TEST_DIR)

# -------------------------------
# Compilation rules
# -------------------------------
# Rule to create object files; here it is clever that if .c and .h are updated, .o is updated; .o updates reference this rule, and .d also updates.
$(BUILD_DIR)/%.o: $(SRC_DIR)/%.c
> @mkdir -p $(@D)
> $(CC) $(CFLAGS) -MD -MP -c $< -o $@

# Include all dependency files
-include $(DEPS)

.RECIPEPREFIX = >

# Submodule configuration
MODULE_NAME := submodule1
SRC_DIR := src
INC_DIR := inc
BUILD_DIR := build
LIB_DIR := ../lib

CC := cc
CFLAGS := -Wall -Wextra -Og -I$(INC_DIR)
AR := ar
ARFLAGS := rv

SRCS := $(shell find $(SRC_DIR) -name '*.c')
OBJS := $(patsubst $(SRC_DIR)/%.c, $(BUILD_DIR)/%.o, $(SRCS))
LIB := $(LIB_DIR)/lib$(MODULE_NAME).a
DEPS := $(OBJS:.o=.d)

.PHONY: all clean

# Default target
all: $(LIB)

# Generate static library
$(LIB): $(OBJS)
> @mkdir -p $(LIB_DIR)
> $(AR) $(ARFLAGS) $@ $^

# Compilation rules
$(BUILD_DIR)/%.o: $(SRC_DIR)/%.c
> @mkdir -p $(@D)
> $(CC) $(CFLAGS) -MMD -MP -c $< -o $@

# Clean rules
clean:
> rm -rf $(BUILD_DIR) $(LIB)

# Automatically include dependency files
-include $(DEPS)